SAKSHI AGARWAL

SAKSHI AGARWAL is currently a Senior ASIC Engineer at Nvidia, where they focus on RTL design and work on the complete RTL to GDS flow. Prior to this role, SAKSHI worked at STMicroelectronics as a Senior Design Engineer and progressed through various positions, including Design Engineer and Engineer Intern. They have expertise in Verilog, VHDL, and digital IP simulations, and possess a solid command of tools such as Cadence Xcelium and Design Compiler.