Urvashi Dhoot

Urvashi Dhoot is a Senior ASIC Engineer at NVIDIA since February 2019, specializing in static timing analysis and circuit analysis for chip timing violations while utilizing EDA tools for engineering change orders. Prior experience includes a role as a SOC Design Engineer at Intel Corporation, where responsibilities included developing simulation models and configuration rules for FPGA Transceiver IP as part of the HSSI group, and earlier as a Component Design Engineering Intern, focusing on static timing analysis and power optimization techniques. Educational background includes a Master’s Degree in Electrical and Electronics Engineering with a concentration in VLSI Design from the University of Southern California and a Bachelor’s Degree from Nagpur University. Dhoot has also held leadership positions, including General Secretary of the Students’ Representative Council at Shri Ramdeobaba Kamla Nehru Engineering College, and participated in various internships involving SCADA software and interdisciplinary research projects.