Ranganathan Sundaram

Ranganathan Sundaram is a Senior Lead Engineer at NXP Semiconductors since April 2020, specializing in SoC Level ATPG for automobile chips, with responsibilities including pattern generation, simulation, and coverage analysis. Prior experience includes serving as a Lead Engineer at UST Global, where Ranganathan focused on IDDQ and Transition Delay pattern generation, and as a Senior Associate Consultant at Infosys, contributing to graphics-related chip designs for mobile processors. Ranganathan began a career in engineering with roles at Masamb Electronics Systems, Wipro Technologies, Vision Krest Embedded Technologies, and NOKIA INDIA, where expertise was developed in design engineering, testing methodologies, and development of HDL code. Ranganathan holds a Master of Science in VLSI from M.S.Ramaiah School of Advanced Studies and a Bachelor's degree in Electrical and Electronics Engineering from Mahendra Engineering College.