Panditharadhya M

Panditharadhya M has over 17 years of experience in ASIC design, currently serving as a Functional Lead and Lead ASIC Design Engineer at Open-Silicon, Inc. since June 2009. Key responsibilities include top-level partitioning, die-size estimation, power planning, and timing closure. Prior to this role, Panditharadhya worked as a Senior ASIC Design Engineer focusing on block-level functionalities and timing closure. Experience includes a position as a Design Engineer at ARM, where contributions involved ARM11 based test-chip implementation and benchmarking ARM processor cores for power, performance, and area. Early career experience includes a trainee role at Texas Instruments. Educational qualifications include an M Tech in VLSI Design and Embedded Systems from SJCE, Mysore, and a BE in Electronics and Communication Engineering from Visvesvaraya Technological University.