Henry Zhang

Henry Zhang has a diverse range of experience in various roles and companies. Henry started their career in 1998 as a Design Engineer at Adaptec and then moved on to Allegro Networks, where they worked as an ASIC Engineer. At Allegro Networks, they were responsible for designing ASIC/FPGAs for switch fabric subsystems for routers. In 2002, they became a Member of Technical Staff at Zettacom, followed by a role as a Sr. Verification Engineer at Matrix Semiconductors, where they focused on the verification of NVM products.

In 2006, Henry joined SanDisk as a Senior Staff Engineer, specializing in logic design and verification for embedded logic in NVM products. Henry contributed to the architectural design, RTL design, and timing closure, leading to multiple successful tapeouts.

In 2013, Henry joined Tabula as a Logic Designer, and then moved to SanDisk as a Logic Designer in 2015. During this time, they gained expertise in logic design for NVM products and led and managed the logic design for Storage Class Memory as a Senior Technologist at Western Digital, which they joined through the SanDisk Acquisition.

Henry's most recent position is as a Senior Principal Design Engineer at Rambus, where they started in 2023.

Henry Zhang earned their Ph.D. in Physics from The University of Texas at Austin from 1984 to 1990. Prior to that, they studied Physics at Peking University from 1980 to 1984. There is no available information about their education at Beidafu or UC Santa Barbara.