Abdul Hameed Akram

FPGA Design Software Validation Engineer at Rapid Silicon

Abdul Hameed Akram has a diverse work experience in the field of FPGA design and software validation engineering. Abdul Hameed is currently working as a Lead FPGA Design Software Validation Engineer at Rapid Silicon since July 2022. In this position, they are responsible for validating FPGA designs and working on compiler validation for different FPGA architectures.

Prior to that, Abdul Hameed worked as an Associate Design Engineer at Rapid Silicon from December 2021 to July 2022. In this role, they were involved in FPGA's BRAM inference and instantiation designs and verification. Abdul Hameed also worked on formal verification using tools like OneSpin and Formality, and automated the flow for compilation and simulation using bash script.

Before joining Rapid Silicon, Abdul Hameed worked at Lampró Méllon as an Associate Design Engineer from October 2020 to November 2021. Prior to that, they served as a Trainee Design Engineer at the same company from January 2020 to September 2020.

Abdul Hameed's work experience also includes a summer internship at Pak Elektron Limited in July 2018, where they gained valuable industry experience.

Overall, Abdul Hameed Akram has demonstrated their expertise in FPGA design, software validation, compiler validation, formal verification, and automation.

Abdul Hameed Akram completed their Bachelor's degree in Electrical Engineering from the National University of Sciences and Technology (NUST) between the years 2014 and 2019. Prior to that, they attended Forman Christian College (A Chartered University) from 2012 to 2014, where they obtained their H.S.S.C degree in Pre-Engineering. In their earlier education, they studied at L.D.A. High School from 2010 to 2012 and completed their S.S.C degree in Matriculation (Science Group).

Furthermore, Abdul Hameed Akram has obtained additional certifications. In March 2021, they successfully completed the SystemVerilog for Design and Verification v20.6 Exam from Cadence Design Systems. Additionally, they also completed the Verilog Language and Application v26.0 Exam from the same institution during the same month and year.

Links

Timeline

  • FPGA Design Software Validation Engineer

    July, 2022 - present

  • Associate Design Engineer

    December, 2021

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