Rajesh G.

Rajesh G. has a wide range of work experience in the engineering field. Rajesh is currently working as a Physical Design Engineer at Rivos Inc. since 2022. Prior to this, they worked at NVIDIA as a Principal Engineer from 2020 to 2022, where they were responsible for floorplanning, design planning, place and route, and timing analysis for GPU chips.

Before joining NVIDIA, Rajesh had a long tenure at Intel Corporation. From 2018 to 2020, they served as a SoC Design Engineer/Full-chip Timing/Floorplan Owner/Syn-APR (Senior Staff Eng), where they were involved in defining backend design, integration, timing/physical verification methodology, and conducting research for efficient design approaches. Prior to that, from 2012 to 2017, they worked as a SoC Design Engineer (Senior Staff Eng) at Intel, focusing on full chip integration, floor planning, implementation of high-speed global fabrics, and timing analysis.

Rajesh's tenure at Intel also includes their role as a Software Engineer/Researcher from 2009 to 2012, where they specialized in the development and implementation of efficient geometric fill algorithms for designing processes. Furthermore, they had started their career as a Design Engineer (Summer Intern) at Intel in 2007, where they worked on designing clock distribution and power gating circuits for an SoC.

Prior to joining Intel, Rajesh gained experience as a Summer Intern at MERL in 2006, where they worked on the low-power implementation of multi-band orthogonal frequency division multiplexing (MBOFDM) ultra-wideband (UWB) radio receiver. Rajesh also worked on designing a low-power Viterbi decoder using dynamic voltage scaling and implemented an adaptive sliding block Viterbi decoder in MATLAB.

Rajesh's early experience includes working as an R&D Engineer at Tejas Networks from 2004 to 2004, where they performed board design, FPGA coding, and designed a tester card for the system control unit card for STM4 equipment. Overall, Rajesh G. has a diverse skill set and a strong background in engineering, particularly in physical design, integration, and timing analysis.

Rajesh G. pursued their education in a chronological manner. Rajesh first attended the Indian Institute of Technology, Delhi from 2000 to 2004, where they earned a Bachelor of Technology (B.Tech.) degree in Electrical Engineering (Power). Following this, they enrolled at Texas A&M University from 2005 to 2006 to complete their Master of Science (MS) degree in Computer Engineering. Finally, Rajesh G. continued their studies at Texas A&M University from 2006 to 2009 and successfully obtained a PhD in Computer Engineering.