Bramh Dev Singh

Bramh Dev Singh is a Mixed Signal Design Engineer at HCLTech, where involvement includes modeling and analysis of Sigma-Delta ADC and Modulator's non-idealities since July 2019. Previous experience includes serving as an internship trainee focused on related engineering tasks. Bramh also contributed as a volunteer at Vidyarthi Vigyan Manthan in February 2020 and at the India International Science Festival in November 2019. Educational qualifications include a Master of Technology in VLSI Design from the Indian Institute of Engineering Science and Technology (IIEST), Shibpur, obtained in 2020, and a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Mahatma Jyotiba Phule Rohilkhand University, completed in 2017.