ChethanKumar K M

ChethanKumar K M is a Layout Design Engineer at Sankalp Semiconductor, with experience as a Project Intern at Wipro and prior internships at Emertxe Information Technologies and Global Academy Of Technology, where involvement included digital design and physical verification using Cadence Tool. ChethanKumar is currently pursuing a Master of Technology in Microelectronics at the Birla Institute of Technology and Science, Pilani, expected to complete in January 2026, and holds a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Global Academy Of Technology, completed in 2022. Pre-University education was completed at Sadvidya Composite PU College, followed by high school education at JP English High School.