Md Khaleel Uddin

Md Khaleel Uddin is a skilled engineering professional with a strong background in VLSI design and layout, currently serving as a Member of Technical Staff at SmartSoC Solutions Pvt Ltd since May 2024. Prior to this role, Md Khaleel worked as a Senior Engineer at SYNAPSE TECHNO DESIGN INNOVATIONS PRIVATE LIMITED and Sankalp Semiconductor, showcasing expertise in both analog and standard cell layout design across various technology nodes, including 7nm to 180nm. Experience includes working as an Analog Layout Designer at ARF Design and as a Layout Design Engineer at SmartPlay Technologies, utilizing industry-standard tools such as Cadence Virtuoso, Genesys, and Mentor Graphics Calibre. Educational qualifications include an M.Tech in VLSI System Design from Nizam Institute of Engineering & Technology and a B.Tech in ECE from VIF College of Engineering and Technology.