Soujanya Patil

Soujanya Patil is currently serving as a Design Engineer 1 at Tessolve, beginning in July 2023, focusing on PDK Runset and component design for Intel customers within the PDK Runset Dev L0QA team. Prior experience includes a role as a PDK Runset QA Engineer at Sankalp Semiconductor from August 2021 to July 2023, where responsibilities involved PDK validation for Intel in L1QA and L2 FEQA teams. Soujanya also completed a project internship at SiANOM Technologies Private Limited in early 2021, developing a CNN model for Active Noise Cancellation aimed at addressing noise issues in the automotive industry. Additionally, a student internship at VI Solutions in mid-2019 involved developing automotive test systems and programming a water level indicator using NI LabVIEW software. Soujanya holds a Bachelor of Engineering in Electronics and Communications Engineering from Basaveshwar Engineering College, completed in 2021, and prior education includes a PUC in Science and SSLC from respective institutions.