Manisekhar Gajula

Manisekhar Gajula is a Senior Design Verification Engineer at CoreIC Technologies Pvt Ltd since August 2024, with prior experience as a Design Verification Engineer at SeviTech Systems Pvt. Ltd. from January 2022 to August 2024, and as a Trainee at Maven Silicon from October 2020 to January 2022. Manisekhar holds a Bachelor of Engineering in Electronics and Telecommunication Engineering from BMS College of Engineering (2016-2020), completed Intermediate in Mathematics, Physics, and Chemistry at Rao's Junior College, Nandyal (2014-2016), and finished 10th grade at Sri Chaitanya Techno School, Nandyal (2013-2014).