Sowjanya Mareddy

Sowjanya Mareddy is an experienced professional in the VLSI domain, currently serving as an Associate III at UST since February 2024. Prior to this role, Sowjanya worked as a Design Verification Engineer at SEVITECH SYSTEMS PRIVATE LIMITED from October 2021 to January 2024, and briefly held the position of Associate Engineering Designer at UST from June 2021 to October 2021. Educational qualifications include a Master of Technology in VLSI Design from Vellore Institute of Technology, a Bachelor of Technology in Electronics and Communication Engineering from Jawaharlal Nehru Technological University Ananthapur, an Intermediate degree in M.P.C from Sri Chaitanya Junior College in Tirupathi, and a Secondary School Certificate from Kiran English Medium High School.