Susheel Sharma

Susheel Sharma is a seasoned Principal Physical Design Engineer at SiFive since April 2021, specializing in RISC Core designs and advanced physical design techniques for multi-million gate chips in 5/7nm nodes. Prior to this, Sharma held the position of Sr. Principal Applications Engineer at Cadence Design Systems, focusing on Genus iSpatial evaluations to optimize power, performance, and area (PPA). With a background as a Consulting Engineer at Marvell, Sharma led physical design efforts for high-frequency chips and guided backend teams through the tapeout process. Experience as a Physical Design Specialist at Synopsys involved complex SoC design at advanced process nodes, and earlier roles included design engineering at various semiconductor companies, culminating in managerial positions at STMicroelectronics. Academic qualifications include a Master of Science in Electronics from the University of Jammu, a Master of Business Administration in Marketing from Indira Gandhi National Open University, and a Master of Science in Electrical Engineering with a focus on ASIC Design & Test from Santa Clara University.