Prit Patel is currently working as an ASIC Physical Design Engineer at SignOff Semiconductors since January 2022. Prior to this, Prit worked as a Graduate Research Assistant at the University of Windsor, focusing on FPGAs in image processing and reconfigurable computing in VLSI and FPGA. Prit also has experience as an Undergraduate Research Assistant at G.H. Patel College of Engineering and Technology, where the research focused on sensor integration and embedded systems for designing a wearable device. Prit holds a MASc in Electrical and Computer Engineering from the University of Windsor and a BE in Electronics and Communication from G.H. Patel College of Engineering & Technology.
January, 2022 - present
ASIC Physical Design Engineer at SignOff Semiconductors
ASIC Physical Design Engineer at SmartSoC Solutions Pvt Ltd
ASIC Physical Design Engineer at SignOff Semiconductors
ASIC Physical Design Engineer at SignOff Semiconductors
ASIC Physical Design Engineer at SmartSoC Solutions Pvt Ltd
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