Mukesh Polimera

Mukesh Polimera is a Staff Engineer at Silicon Labs since October 2023, with previous experience as a Senior DFT Engineer at Intel Corporation from January 2019 to October 2023, and as an MTS - DFT at Rambus from August 2017 to January 2019. Prior roles include DFT Engineer positions at Aricent and Soctronics. Mukesh Polimera specializes in DFT implementation, MBIST, JTAG, SCAN, compression, pattern generation, simulations, and tester support. Academically, Mukesh Polimera holds a Master of Technology in Microelectronics from the Birla Institute of Technology and Science (2021-2023), an Engineer's Degree in Electrical, Electronics and Communications Engineering from IETE (2013-2017), and a Special Diploma in Electronics with specialization in Communication Engineering from the Govt Institute of Electronics, Secunderabad (2009-2012).