Zhiying Zhang

Senior Analog Design Engineer at Silicon Line

Zhiying Zhang has been working in the semiconductor industry since 2006. Zhiying began their career at Freescale Semiconductor as an Analog Design Engineer. In 2008, they moved to ST-Ericsson as a Lead Analog Design Engineer. In 2012, they were hired by NXP Semiconductors as a Principal Engineer, RF/Analog Design. Since 2014, they have been employed by Silicon Line GmbH as a Senior Analog Design Engineer.

Zhiying Zhang attended Zhejiang University from 2000 to 2004, earning a BSEE in Electrical & Electronic Engineering. Zhiying then returned to Zhejiang University from 2004 to 2006 and obtained an MSEE in Circuits and Systems.

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Timeline

  • Senior Analog Design Engineer

    July, 2014 - present