Venkateswara Rao Arumilli

Venkateswara Rao Arumilli has extensive work experience in the field of physical design engineering. Venkateswara Rao started their career at SMSC in 2007, where they worked as a Physical Design Engineer. Their responsibilities included implementing and executing the PNR flow in ICC using UPF methodology, conducting IR and EM analysis, and performing STA. Venkateswara Rao also worked on the implementation of PHY Macros for DDR2-800 Mbps. In 2010, they joined Rapid Bridge as a PD and worked there for a year. In 2011, they moved to Qualcomm and held several roles, including Engineer, Senior Engineer, Senior Lead Engineer, and Staff Engineer. Venkateswara Rao worked on various projects and gained expertise in their field. In 2019, they joined AMD as a Senior Member of Technical Staff, where they served as the Execution Scheduler and Decoder Unit PD lead for x86 Arch. Venkateswara Rao was also responsible for the Timing Sign-off lead for the SOC Core Chiplet Die (CCD). Currently, Venkateswara Rao Arumilli is working at SiMa.ai as a Physical Design Engineer.

Venkateswara Rao Arumilli holds a Master of Technology (MTech) degree in Microelectronics from the Birla Institute of Technology and Science, Pilani. Prior to this, they completed a Bachelor of Engineering (BE) in Electrical, Electronics and Communications Engineering from the University of Madras. However, specific start and end years for both degrees were not provided.