E. Surendhar

Physical Design Engineer at SmartSoC Solutions Pvt Ltd

E. Surendhar is a skilled Physical Design Engineer with experience at SmartSoC Solutions Pvt Ltd since February 2022, where three 5nm technology projects for AMD have been completed and a Qualcomm project is currently underway. Prior to this role, E. Surendhar served as an Assistant Professor at MTIET from January 2020 to February 2022, teaching subjects such as digital electronics, integrated circuits, and VLSI. Additional experience includes a position at Takshila Institute of VLSI Technologies from June 2021 to November 2021, where knowledge of physical design flow was gained, and various tasks including floor plan and routing were implemented using Synopsys ICC tools. E. Surendhar holds a Master of Technology (MTech) degree in VLSI from Nishitha Institute of Technology and Science, completed in December 2018.

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