Vinay Jakkala

Vinay Jakkala is a Design Verification Engineer at SmartSoC Solutions Pvt Ltd since August 2022, previously completing an internship at Central Institute of Tool Design where projects included an automatic door lock system and a low power, high speed configurable adder for approximate computing in the VLSI domain. Vinay Jakkala earned a Bachelor of Technology (BTech) in Electrical, Electronics, and Communications Engineering from MVSR Engineering College, graduating in 2022.