Ian Vidler

Ian Vidler has more than 20 years of experience in RFIC design engineering. Ian started their career in 1999 at Cadence Design Systems, where they worked as a Cadence Senior Engineer, designing Analog (AMS) and Digital Soc. Designs for customers including digital (DVB-T) / Analog TV, hearing aid, Bluetooth etc. In 2005, they moved to Elonics, where they worked as a Senior Design Engineer until 2012. At Sequans Communications, where they worked as a Principal RFIC Design Engineer from 2012 to 2017, they contributed to developing LTE chipsets. From 2017 to 2021, they worked at Satixfy UK as a Principal RFIC Design Engineer and was the Technical lead / Principal Designer of a small team and block designer of a CMOS SOI RFIC chip used for Antenna phased arrays. Microwave frequencies Satellite communications (IOT). At Wireless Innovative MMIC (WIMMIC), they served as a Principal RFIC Design Engineer from 2021 to 2023, contributing to the design of 5G wireless infrastructure. Currently, they are working as a Principal RFIC Design Engineer at Sofant Technologies, where they are working on developing RFIC modules for 5G infrastructure.

Ian Vidler earned a Bachelor of Engineering degree in Electronics & Electrical Engineering from the University of Plymouth between 1984 and 1988. Later, between 1992 and 1994, they completed their Master of Science degree in Digital System Engineering from Heriot-Watt University.