Deepak Pepalla

Deepak Pepalla is a passionate digital ASIC and FPGA designer currently serving as a Staff ASIC Design Engineer at Synopsys Inc., focusing on DDR PHY IP. With approximately five years of experience in the semiconductor industry, Deepak previously held roles at AMD, Western Digital, and Axiado, where they specialized in low-power design and hardware security. Deepak's educational background includes a Master of Science in Electrical and Computer Engineering from the University of Florida and is currently pursuing a Master’s degree in Computer Science at Harrisburg University of Science and Technology. Deepak's skill set encompasses various tools and programming languages, including Verilog and System Verilog, as well as expertise in machine learning and hardware security.