GAURAV BARANWAL

Gaurav Baranwal is a Staff ASIC Digital Design Verification Engineer at Synopsys Inc, where they have held several positions since 2023. Gaurav completed a Master of Technology in Electronics and Communications Engineering from Jamia Millia Islamia University in 2018, achieving a notable CGPA of 9.57. Prior to their current role, Gaurav gained experience as an intern at Truechip Solutions in 2019. With a strong interest in VLSI, Analog Design, and Digital Circuitry, Gaurav demonstrates a dynamic and enthusiastic approach to their work in the technical segment of the electronics field.