Jayanth Bandaru is a Principal Engineer in Physical Design at Synopsys Inc., with over 18 years of experience in the industry. They have expertise in PDN activities, SoC power analysis, and hands-on experience with multiple tape-outs for various foundries at advanced process nodes, including 3nm and 5nm. Previously, Jayanth held positions as a Senior Staff Design Engineer at Xilinx and as a Senior Design Engineer at Tundra Semiconductors, focusing on ASIC physical implementation and power integrity. They earned a B.Tech in Electronics & Instrumentation from Gandhi Institute of Technology & Management and a Master of Technology in Digital Systems from JNTU Anantapur.
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