Josee Cayer P.eng.

Josee Cayer P.Eng. PMP is an experienced engineering professional specializing in ASIC design verification and FPGA design, currently serving as an ASIC Design Verification Engineer at Synopsys Inc since April 2024. Prior roles include FPGA Designer positions at MDA and Syntronic, where Josee developed advanced testing environments for LIDAR systems and contributed to various FPGA architectures. Previous project management experience encompasses overseeing the development of an L-Band Iridium Satellite Data Unit at Satcom Direct and managing multiple R&D projects at Fidus Systems. Josee holds a B.Eng in Communications Engineering and a B.A. Hon in Linguistics and Applied Language Studies from Carleton University.