Panshul Jugran

Panshul Jugran is currently a Principal Engineer at Synopsys Inc., specializing in emulation and transactor solutions for PCIe, CXL, UCIe, and UAL. With over 10 years of experience in verification, pre-silicon validation, and post-silicon validation, Panshul has developed expertise in various protocols and HDL languages, including Verilog and System Verilog. Their previous roles include positions at Freescale Semiconductor, AMD, Cadence Design Systems, and Mentor Graphics, where they contributed to critical projects in silicon validation and emulator solutions. Panshul holds a Bachelor's degree in Electronics and Telecommunication from the University of Mumbai and an advanced diploma in VLSI from RV VLSI.