Shiva Cheerala is a Senior Engineer in A&MS Layout Design at Synopsys Inc., currently focusing on high-speed SerDes layout designs. They have over four years of experience in Analog/Mixed-Signal Layout Design, having previously worked on Intel SERDES projects at Sankalp Semiconductor from 2021 to 2024. Shiva holds a Bachelor of Technology in Electrical and Electronics Engineering from JNTUH College of Engineering Jagityala, as well as a strong academic background from other institutions.
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