Varun Ranganath

Varun Ranganath is a Layout Design Sr Staff Engineer at Synopsys, specializing in LPDDR6 PHY design. They have extensive experience in RF/Analog layout design, having previously worked at Qualcomm and Tessolve, where they handled various analog and high-frequency core blocks. Varun holds a Bachelor of Engineering in Electronics and Communications Engineering from Visvesvaraya Technological University, completed in 2015. Their expertise includes physical verification checks, graphical parameterized cell creation, and proficiency in Cadence Virtuoso Layout Editor.