Vengal Reddy has a robust background in digital design and engineering, with experience spanning multiple companies since 2017. Initial experience included a role as LD at VEDAIIT, followed by a position at Soctronics where Vengal Reddy advanced from Design Engineer 1 to Design Engineer 2 from November 2018 to August 2020. Subsequently, a tenure at Intel Corporation as a System-on-Chip Design Engineer lasted from August 2020 to February 2023. Currently, Vengal Reddy serves as an ASIC Digital Design Engineer Sr I and ASIC Digital Design Staff Engineer at Synopsys Inc from February 2023 to February 2024. Education includes a B.Tech in Electronics & Communication from Annamacharya Institute of Technology & Sciences and an ongoing Master of Technology in Microelectronics through BITS Pilani Work Integrated Learning Programmes. Schooling was completed at Jawahar Navodaya Vidyalaya Kadapa and Sri Gayatri Jr College, Tirupati.
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