VVSN Murthy Jyothula is a Senior Engineer at Synopsys in Hyderabad, specializing in Analog Mixed Signal layout design with six years of experience across various technology nodes, including Samsung 3nm and Intel 22nm. They previously worked as an Analog Layout Engineer at Aricent and as an AMS Layout Design Engineer-2 at INVECAS. VVSN holds a Bachelor of Technology degree in Electronics & Communication Engineering from Aditya College of Engineering & Technology, where they studied from 2013 to 2017.
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