Jayanth Bharadwaj

Jayanth Bharadwaj is a Physical Design Engineer at Tenstorrent since February 2024, previously serving as a Teaching Assistant for the Semiconductor Devices course at the University of Minnesota from August 2023 to January 2024. Jayanth gained experience as a CPU Core Physical Design Intern at AMD, focusing on NID nets, DRCs, and automating multi-stage clock gating. Prior to that, Jayanth worked as a Memory Design Intern at GlobalFoundries, developing layouts for Model Hardware Correlation test chips and creating schematics for various technologies. Jayanth holds a Master of Science in Electrical Engineering with a specialization in VLSI from the University of Minnesota and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Visvesvaraya Technological University.