Jeffrey Benagh

Jeffrey Benagh has extensive experience in the field of engineering, particularly in ASIC and FPGA design. Since April 1994, Jeffrey has been with Teradyne, progressing to the role of System Architect in 2005, where significant contributions include the architecture of multiple large SOC FPGAs for Automated Test Equipment (ATE) applications and the integration of embedded processors into SOC FPGA designs. Prior to Teradyne, Jeffrey worked at Raytheon from 1990 to 1994 as a Member of Technical Staff, focusing on the design and integration of ASIC and PC board products for digital signal processing applications. Jeffrey's early career included a co-op position at Bell-Northern Research. Jeffrey holds a Bachelor of Science degree in Electrical Engineering from Cornell University, obtained in April 1990.