Prakash Palanisamy

Prakash Palanisamy is a Senior Layout Engineer at Texas Instruments since December 2021, bringing extensive experience in the semiconductor industry. Previous roles include serving as Technical Lead at Pactron Inc. from August 2015 to December 2021, where responsibilities involved designing high-speed DUT boards and probe cards, as well as deep knowledge of DFM&DFA processes and IPC regulations. Prior to Pactron, Prakash was a Senior Design Engineer at Tessolve Semiconductor PVT LTD from August 2010 to August 2015, specializing in high-quality ATE and system boards with simulation compliance. Earlier in the career, a role as Trainee Process Associate at Sterlite Technologies involved fiber optic cable production. Educational qualifications include a Master of Science in Applied Electronics from PSG College of Technology and a Bachelor’s Degree in Electronics from Bharathiyar University. EDA skills include Allegro16.