Shubham Saurabh

Shubham Saurabh is a seasoned engineer with extensive experience in the design and validation of semiconductor technologies. Currently serving as a Senior Design Engineer at Texas Instruments since December 2021, Shubham is responsible for creating the Cadence Palladium Z1 compile platform for Pre-Silicon validation and developing Verilog HDL models for analog IPs. Previously, Shubham held senior and design engineer roles at NXP Semiconductors from October 2016 to December 2021, focusing on ARM Cortex cores and automotive communication protocols. Earlier, Shubham worked at Freescale Semiconductor in functional validation roles for automotive products. Shubham holds a Bachelor of Engineering in Electronics and Communications Engineering from Birla Institute of Technology, Mesra, and has a solid educational foundation with a focus on science and technology.