Larry Calabio

Larry Calabio has over 20 years of work experience in the field of hardware engineering. Larry began their career in 1998 as an R&D Hardware Technician/System Integration at Fibex Systems, which was later acquired by Cisco Systems. In 2000, they became a Hardware Engineering Technician at Cisco Systems. Larry then moved to Valo, Inc. in 2002 as a Hardware Test Engineer. In 2004, they joined Klamath Networks as a Hardware Test Engineer. Larry was a Member of Technical Staff at Turin Networks/Force10 Networks from 2005 to 2009. From 2009 to 2013, they were a Hardware Development Engineer at Dell-Force10 (Former Turin Networks). Larry currently works as an Operation Test Engineer at Tibit Communications, Inc. since 2019. During their time at Ciena, they worked on schematic design/layout using Cadence Concept Design Entry HDL for Ciena’s Waveserver AI 10-Channel optical Mux/DeMux pluggable module with integrated OTDR (CMD10) and Ciena’s 6500 100G optical transponder (Optical Whitebox) using NEL DSP chipsets. Larry also worked on schematic design/layout using Cadence Capture OrCAD CIS for Cyan’s Z-series packet switch linecard (PSW-10G20, PSW-100G2W) and optical line amplifier (OLA). Larry designed these linecards using High Speed CPU (Zilinx Zynq UltraScale MPSoCs, Freescale P2020, P1015), Broadcom chipsets (1/10/40 PHY/MAC, Arad+ 200G Packet Processor/Traffic Manager), NEL chipsets, Marvell PHY, etc.

Larry Calabio attended Santa Rosa Junior College from 1994 to 1997, where they earned an Associate of Science in Electronic Technology Accelerated Major.