Renxin Xia

Renxin Xia has over 25 years of experience in the technology industry. From 1996 to 1999, Xia was the Design Manager at ESS Technology, where they were responsible for architecture and design of a DSP for modems and a multimedia processor for video encoding and decoding. From 1999 to 2001, Xia was the Acting VP Engineering at Centrality Communications, where they were the first person recruited by the Founder/CEO to launch the new start-up and was responsible for building the engineering team and execution. From 2001 to 2017, Xia was with Altera, where they held three roles: Director, High-Performance FPGA Development, Director, ASIC Products, and Director, IC Design. In 2017, Xia joined SiFive as VP Engineering, where they were responsible for all engineering organization and execution and for developing an automation framework for various aspects of SOC development. From 2018 to 2022, Xia was the Chief of Staff to the CEO at Cadence Design Systems. In 2022, Xia joined Untether AI as VP Hardware.

Renxin Xia received an MBA from the University of California, Berkeley, Haas School of Business in 2005. Prior to that, they earned a MS and BS in Electrical Engineering from Stanford University between 1991 and 1996.