Shigeki Shimomura

Shigeki Shimomura has over 28 years of work experience. Shigeki began their career in 1993 as a Design Engineer at Intel Corporation, where they worked on custom digital circuit and SRAM cache designs on 0.7um through 130nm process. In 2001, they moved to Toshiba STI Design Center as a Design Manager. Later that year, they returned to Intel Corporation as a Sr. Design Engineer. In 2015, they joined TSMC North America as a Technical Manager. In 2016, they became a Principal Hardware Engineer at Oracle, where they designed 10/7nm L3 Cache tag block designs for the next generation SPARC microprocessors. In 2017, they joined Western Digital as a Technologist, R&D Engineering. In 2019, they returned to TSMC North America as a Technical Manager. Currently, they are a Senior SRAM Design Engineer at Untether AI.

Shigeki Shimomura received their Bachelor of Science in Electrical and Electronics Engineering from Tohoku University in 1991. Shigeki then pursued a Master of Science in Electrical and Electronics Engineering at Tohoku University, which they completed in 1993.