satish srerambatla

Satish Srerambatla began their work experience in 2010 at Sony India Software Centre as a Senior Software Engineer in the Firmware group. In this role, they worked on the video input module, including components like HDMI, CVBS, and PC connections. satish also played a part in the On Screen Display (OSD), Encoder, and Non-linear Scaling modules.

In 2015, Satish joined Qualcomm as an ASIC Design Engineer. satish was a part of the L3 cache design team and worked on the chip-to-chip filter (C2CF) project. Additionally, they supported the performance monitor block for L3 cache and contributed to measuring the cache's performance metrics. As an intern, they also assisted with the At Speed Trace block for caching the bus trace and was actively involved in design debugging and providing RTL fixes.

Starting in 2018, Satish joined Intel Corporation as a CPU RTL Design Engineer. satish'sresponsibilities included working on the micro-architecture and RTL design of multiple clusters in the Out-of-Order (OOO) unit for Intel's next-generation CPUs. satish collaborated with performance modeling, verification, and implementation teams to optimize designs for power, performance, and frequency.

Most recently, Satish transitioned to Ventana Micro Systems in 2023, where they currently hold the position of Staff Engineer. No specific details regarding their roles and responsibilities at Ventana Micro Systems are provided.

Satish Srerambatla completed their Bachelor's degree in Electrical, Electronics, and Communications Engineering from the National Institute of Technology Warangal from 2006 to 2010. Later, they pursued a Master's degree in VLSI and Microarchitecture from North Carolina State University from 2013 to 2015.