Jelena Eremic

Jelena Eremic has a strong background in engineering, specifically in design verification and functional verification. Jelena started their career in 2003 as a project associate at the University of Novi Sad, Faculty of Technical Sciences. From there, they worked as an FPGA Design and Verification Engineer at MicronasNIT LLC from 2004 to 2008, and then at RT-RK Computer Based Systems LLC from 2008 to 2012. Jelena continued their career at Frobas d.o.o. as a Digital Design and Functional Verification Engineer from 2012 to 2015. In 2015, Jelena joined ELSYS Eastern Europe as a Functional Verification Engineer and remained with the company until 2020. Currently, they hold the position of Design Verification Engineer at Veriest, where they started in April 2020.

Jelena Eremic obtained an MSc degree in Computer Engineering from the University of Novi Sad, Faculty of Technical Sciences, specializing in the Department of Computing and Automation. The specific years of enrollment and completion are not provided.