Phani Srinivas M.

Phani Srinivas M. has a strong background in physical design engineering, with experience in both ASIC and CPU subsystems. They have worked on complex high-speed processor blocks, including 6nm technology, and have a deep understanding of constraints development for timing convergence. They have contributed to multiple tape-outs in various nanometer designs, including 14nm, 12nm, and 7nm. Phani is skilled in all aspects of the ASIC flow, including floor planning, P&R, extraction, and IR Drop Analysis. They have experience constructing clocks on multi-clock, synchronous, and asynchronous clock domains. Phani has also demonstrated their ability to make strategies for congestion control and are proficient in STA analysis. They are skilled in scripting and automation, having developed several shell and Tcl scripts to enhance productivity.

Phani Srinivas M. holds a Bachelor of Technology (BTech) degree in Electrical, Electronics, and Communications Engineering from Jawaharlal Nehru Technological University. Before pursuing their BTech, Phani completed their Intermediate education at Narayana Junior College, specializing in Mathematics, Physics, and Chemistry. Prior to that, they attended U H S for high school. Additionally, Phani has obtained several certifications, including the Cadence RTL-to-GDSII Flow v4.0 Exam and the Cadence Student Ambassador Exam from Cadence Design Systems. Phani Srinivas also holds an Advanced Diploma in Physical Design from the Institute of Silicon Systems Pvt. Ltd. Furthermore, Phani has an undisclosed certification in Cadence Certified Static Timing Analysis.