Yuriy Mestman

Yuriy Mestman is an experienced engineer specializing in hardware development and digital signal processing. Currently serving as a HW Development Engineer in RTL Design at Aeva since March 2022, Yuriy previously worked as a Staff FPGA System Design Engineer at Xilinx, focusing on digital logic and signal-processing datapath design. Prior roles include Staff FPGA Design Engineer at Vave Health, where Yuriy worked on medical devices, and DSP Algorithm IP/Digital Design Engineer at Intel Corporation, contributing to 5G specifications. Yuriy's background also includes positions at Raytheon, Audience, Inc., NXP Semiconductors, Zoran Corporation, and Proteus Biomedical, Inc., with extensive expertise in VHDL, Verilog, and the development of signal-processing algorithms. Yuriy holds an MS and a BS in Electrical Engineering from San Jose State University.