Siddalinga Aland

Siddalinga Aland is a Principal Physical Design Engineer at Ampere since March 2019, specializing in the overall Physical verification process, including PDK evaluation and multi-hierarchy verification. Previous roles include Senior Staff Design Engineer, focusing on full chip integration and verification, and Staff Physical Design Engineer at Broadcom Limited, where involvement in full chip ASIC verification and 7nm physical design took place. Additional experience includes IC Mask Design Engineer at Xilinx and various roles at companies such as SmartPlay Technologies, Qualcomm India, and Intel Corporation, encompassing both analog and digital designs. Siddalinga holds an M.Tech in VLSI Design & Embedded Systems and a BE in Electronics & Communication.