Chirag Panchal

Chirag Panchal has a diverse work experience in the field of physical design. Chirag currently holds the position of Technical Lead - Physical Design at Astera Labs since November 2022. Prior to this, they worked at Juniper Networks for 5 years, starting as an Asic Engineer 3 - Physical Design and later transitioning to the role of Asic Engineer 4 - Physical Design. During their time at Juniper Networks, they contributed to the successful tape-outs of multiple 7nm networking chips and was involved in various aspects of CAD team responsibilities, including PNR/sign-off flow development, Full Chip flat extraction, and Full Chip IR & EM flow development.

Before working at Juniper Networks, Chirag held the position of Physical Design Manager and Technical Lead at SeviTech Systems Pvt. Ltd. In these roles, they played a key role in expanding the physical design team from 1 to 25 members within a year. Chirag also contributed to the successful tape-out of a 16nm GPU chip and was responsible for block design level floorplanning, Place and Route, CTS, physical verification, functional verification, and analysis tasks.

Prior to SeviTech Systems, Chirag worked as a Senior Physical Design Engineer at Synapse Design Inc., where they participated in the successful tape-out of a 16nm networking chip. Chirag was involved in various stages of the physical design process, including floorplanning, Place and Route, timing closure, and design physical verification.

Chirag's early work experience includes their role as a Physical Design Engineer at eInfochips, where they contributed to the successful tape-outs of multiple networking chips. Chirag was proficient in the complete netlist to GDS design flow and was involved in all stages of the physical design process. Chirag also briefly worked as a Physical Design Trainee at eiTRA (eInfochips Training & Research Academy).

Overall, Chirag Panchal has extensive experience in physical design, with a focus on networking chips. Chirag has a strong background in various aspects of the physical design process and has contributed to the successful tape-outs of multiple chips throughout their career.

Chirag Panchal completed their Diploma in Electronics & Communications from B & B Institute Of Technology between 2005 and 2008. Chirag later pursued their B.Tech degree in Electronics and communication engineering from Ganpat University, which they completed from 2008 to 2011.