Jake Hu

Jake Hu has extensive work experience in the field of IC design and engineering. Jake started their career as an Electrical Design Engineer at Siemens Manufacturing and Engineering Center Shanghai in 1995. After that, they worked as a Hardware Design Engineer at GE Fanuc Automation for one year. In 1998, they joined Agere Systems as an ASIC Design Engineer, where they were involved in RTL design, verification, synthesis, and formal verification. Jake also gained experience in device bring-up and bench validation. In 2006, Jake Hu joined Texas Instruments as a Senior Digital Design Engineer. Jake worked on various projects, including the design of an Analog PLL with a clock frequency of up to 1GHz. Their responsibilities included leading the front-end and back-end design, verification, and managing the entire design flow from RTL coding to GDSII. In 2019, they joined ams AG, first as a Senior Staff IC Design Engineer and later promoted to Principal Engineer. The details of their roles and responsibilities at ams AG are not specified.

Jake Hu earned a Bachelor of Engineering (BE) degree in Electromechanics from the University of Science and Technology of China. Jake attended the university from 1990 to 1995. After that, they pursued a Master of Science (MS) degree in Electrical Engineering (EE) from Dartmouth College, where they studied from 1996 to 1998.

In terms of additional certifications, Jake obtained several certifications from Cadence Design Systems in April 2023. These include the following:

- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis vIC6.1.8 Exam

- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis vIC6.1.8/ICADVM20.1 Exam

- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners vIC6.1.8/ICADVM20.1 Exam (x2)