Ke Jiang

Ke Jiang has over 20 years of work experience in various roles as a senior hardware design engineer and project lead. Ke began their career at Bell Labs (China) as a Member of Technical Staff before moving on to IC Media as a Senior Design Engineer. Ke then joined Magnachip as a Senior Design Engineer and later worked as a Senior Design Engineer at Altasens. Ke Jiang also served as a CMOS Sensor Project Lead at Fudan Microelectronics. Currently, they are working as a Senior Hardware Design Engineer at Arecont Vision. Ke Jiang is highly experienced and has a strong background in hardware design engineering.

Ke Jiang attended Fudan University, although the specific years and degree/field of study are not provided. Prior to university, Ke Jiang attended SheHong High School, but again, no years or specific details are given.