Justina Provine

Justina Provine is a distinguished engineer at Astera Labs since August 2021, specializing in the architecture and leadership of CXL memory expansion SoCs and security solutions across multiple product lines. Prior to this role, Justina served as a multitalented engineer at Pensando Systems from January 2017 to August 2021, where significant contributions included leadership in ASIC architecture, design, and verification/validation of P4 datapath and DMA engines, alongside coordination of discussions among various functional groups. Justina also held the position of principal engineer at Palo Alto Networks for one year, followed by a technical leader role at Cisco Systems from November 2001 to December 2015, and began the career as a hardware engineer at Alcatel from 1999 to 2001, focusing on ASIC design.