Jeroen van Loon

Jeroen van Loon has over 20 years of experience in the semiconductor industry. Jeroen began their career in 1992 as an IC Design Engineer at Philips Research, where they developed digital circuits for audio and video signal processor ICs. In 1998, they joined NXP Semiconductors as a Hardware Architect, responsible for the specification and implementation of subsystems based on RISC processors. Jeroen also served as a Senior Design Engineer, where they were the technical lead responsible for the implementation of complex mixed signal SoCs in the area of mobile, automotive, and consumer applications. In 2009, they moved to Virage Logic as a Physical Architect, working on benchmarking activities for RISC processors. Jeroen then moved to Synopsys in 2010, where they held the same role. In 2012, they joined Intel Corporation as a Senior Physical Design Engineer. In 2020, they joined Bitfury as a Physical Design Team Lead, a role they currently hold at Axelera AI, which they joined in 2021.

Jeroen van Loon attended Hogeschool Eindhoven from 1988 to 1991, where they obtained a Bachelor of Science in Electronics/ Digital IC Design.