Akshay Pratap

Akshay Pratap is a Senior Principal Engineer with experience in IP Design and Functional Verification using Verilog, System Verilog, Perl, and Shell Scripting. Starting as a Trainee at CEERI Pilani, Akshay has worked their way up through positions at companies such as Wipro Technologies, Tejas Networks, LSI Corporation, and currently at Cadence Design Systems. Akshay holds a Bachelor of Technology (B.Tech.) degree from NIT Jalandhar.