Vatsal Patel is an experienced engineer with a strong background in semiconductor design and verification. Vatsal began the career as a Software QA Analyst at Indigo in 2014 and progressed to various roles, including Automation Developer at Citi and Embedded Developer at Molex. Notable experiences include internships as a Physical Design Engineer at NVIDIA and a Vision Processor Digital Design and Verification Engineer at NXP Semiconductors. In a more advanced capacity, Vatsal served as a Sr. Silicon Design Engineer at AMD, focusing on RTL design and various analyses. Currently, Vatsal works as an ASIC Design Engineer at Ciena, specializing in synthesis and handoff processes. Vatsal holds a degree in Electrical Engineering from the University of Waterloo.
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