Guénolé Lallement

Guénolé Lallement is a seasoned engineer specializing in hardware design and machine learning applications. Currently serving as Lead Physical Design Engineer at Efficient Computer since March 2023, Guénolé is focused on developing next-generation edge AI chips. Prior experience includes a role as Silicon HW Design Engineer at Meta, contributing to mixed-reality device advancements, and a Postdoctoral Research Fellow position at Stanford University, where Guénolé researched optimal computing organization for various domains. Earlier roles involved an Industrial PhD at IM2NP and STMicroelectronics, developing power-efficient computing systems and enhancing SoC capabilities. Guénolé holds a PhD in Electrical and Electronics Engineering from Aix-Marseille University and additional degrees from prestigious institutions including Imperial College London and Télécom Paris.